Merge branch 'test/aligned_tests' into dev

This commit is contained in:
Jack Wills
2024-07-27 09:14:39 +00:00
2 changed files with 218 additions and 221 deletions
+6 -6
View File
@@ -2091,9 +2091,9 @@ mod tests {
let result = app_data.get_width(); let result = app_data.get_width();
let expected = Columns { let expected = Columns {
name: (Header::Name, 11), name: (Header::Name, 11),
state: (Header::State, 11), state: (Header::State, 9),
status: (Header::Status, 16), status: (Header::Status, 9),
cpu: (Header::Cpu, 7), cpu: (Header::Cpu, 6),
mem: (Header::Memory, 7, 7), mem: (Header::Memory, 7, 7),
id: (Header::Id, 8), id: (Header::Id, 8),
image: (Header::Image, 7), image: (Header::Image, 7),
@@ -2113,9 +2113,9 @@ mod tests {
let result = app_data.get_width(); let result = app_data.get_width();
let expected = Columns { let expected = Columns {
name: (Header::Name, 28), name: (Header::Name, 28),
state: (Header::State, 11), state: (Header::State, 9),
status: (Header::Status, 16), status: (Header::Status, 9),
cpu: (Header::Cpu, 7), cpu: (Header::Cpu, 6),
mem: (Header::Memory, 7, 7), mem: (Header::Memory, 7, 7),
id: (Header::Id, 8), id: (Header::Id, 8),
image: (Header::Image, 7), image: (Header::Image, 7),
+81 -84
View File
@@ -1359,44 +1359,6 @@ mod tests {
// Container summary panel // // Container summary panel //
// *********************** // // *********************** //
// Check that the correct solor is applied to the state/status/cpu/memory section
fn check_expected(expected: [&str; 6], w: u16, _h: u16, setup: &TuiTestSetup, color: Color) {
for (row_index, result_row) in get_result(setup, w) {
let expected_row = expected_to_vec(&expected, row_index);
for (result_cell_index, result_cell) in result_row.iter().enumerate() {
assert_eq!(result_cell.symbol(), expected_row[result_cell_index]);
match (row_index, result_cell_index) {
// border
(0 | 5, _) | (1..=4, 0 | 129) => {
assert_eq!(result_cell.fg, Color::LightCyan);
}
// name, id, image column
(1..=3, 4..=14 | 78..=98) => {
assert_eq!(result_cell.fg, Color::Blue);
}
// state, status, cpu, memory column of the first row
(1, 15..=77) => {
assert_eq!(result_cell.fg, color);
}
// state, status, cpu, memory column
(2..=3, 15..=77) => {
assert_eq!(result_cell.fg, Color::Green);
}
// rx column
(1..=3, 99..=108) => {
assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193));
}
// tx column
(1..=3, 109..=118) => {
assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140));
}
_ => assert_eq!(result_cell.fg, Color::Reset),
}
}
}
}
#[test] #[test]
/// No containers, panel unselected, then selected, border color changes correctly /// No containers, panel unselected, then selected, border color changes correctly
fn test_draw_blocks_containers_none() { fn test_draw_blocks_containers_none() {
@@ -1454,7 +1416,7 @@ mod tests {
#[test] #[test]
/// Containers panel drawn, selected line is bold, border is blue /// Containers panel drawn, selected line is bold, border is blue
fn test_draw_blocks_containers_some() { fn test_draw_blocks_containers_selected_bold() {
let (w, h) = (130, 6); let (w, h) = (130, 6);
let mut setup = test_setup(w, h, true, true); let mut setup = test_setup(w, h, true, true);
@@ -1533,7 +1495,7 @@ mod tests {
"│ container_2 ✓ running Up 2 hour 00.00% 0.00 kB / 0.00 kB 2 image_2 0.00 kB 0.00 kB │", "│ container_2 ✓ running Up 2 hour 00.00% 0.00 kB / 0.00 kB 2 image_2 0.00 kB 0.00 kB │",
"│ container_3 ✓ running Up 3 hour 00.00% 0.00 kB / 0.00 kB 3 image_3 0.00 kB 0.00 kB │", "│ container_3 ✓ running Up 3 hour 00.00% 0.00 kB / 0.00 kB 3 image_3 0.00 kB 0.00 kB │",
"│ │", "│ │",
"╰────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────╯", "╰────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────╯"
]; ];
let fd = FrameData::from((setup.app_data.lock(), setup.gui_state.lock())); let fd = FrameData::from((setup.app_data.lock(), setup.gui_state.lock()));
@@ -1546,6 +1508,7 @@ mod tests {
for (row_index, result_row) in get_result(&setup, w) { for (row_index, result_row) in get_result(&setup, w) {
let expected_row = expected_to_vec(&expected, row_index); let expected_row = expected_to_vec(&expected, row_index);
for (result_cell_index, result_cell) in result_row.iter().enumerate() { for (result_cell_index, result_cell) in result_row.iter().enumerate() {
assert_eq!(result_cell.symbol(), expected_row[result_cell_index]); assert_eq!(result_cell.symbol(), expected_row[result_cell_index]);
@@ -1555,19 +1518,19 @@ mod tests {
assert_eq!(result_cell.fg, Color::LightCyan); assert_eq!(result_cell.fg, Color::LightCyan);
} }
// name, id, image column // name, id, image column
(1..=3, 4..=14 | 78..=98) => { (1..=3, 4..=17 | 71..=91) => {
assert_eq!(result_cell.fg, Color::Blue); assert_eq!(result_cell.fg, Color::Blue);
} }
// state, status, cpu, memory column // state, status, cpu, memory column
(1..=3, 15..=77) => { (1..=3, 18..=70) => {
assert_eq!(result_cell.fg, Color::Green); assert_eq!(result_cell.fg, Color::Green);
} }
// rx column // rx column
(1..=3, 99..=108) => { (1..=3, 92..=101) => {
assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193)); assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193));
} }
// tx column // tx column
(1..=3, 109..=118) => { (1..=3, 102..=111) => {
assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140)); assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140));
} }
_ => assert_eq!(result_cell.fg, Color::Reset), _ => assert_eq!(result_cell.fg, Color::Reset),
@@ -1612,6 +1575,44 @@ mod tests {
} }
} }
// Check that the correct colour is applied to the state/status/cpu/memory section
fn check_expected(expected: [&str; 6], w: u16, _h: u16, setup: &TuiTestSetup, color: Color) {
for (row_index, result_row) in get_result(setup, w) {
let expected_row = expected_to_vec(&expected, row_index);
for (result_cell_index, result_cell) in result_row.iter().enumerate() {
assert_eq!(result_cell.symbol(), expected_row[result_cell_index]);
match (row_index, result_cell_index) {
// border
(0 | 5, _) | (1..=4, 0 | 129) => {
assert_eq!(result_cell.fg, Color::LightCyan);
}
// name, id, image column
(1..=3, 4..=17 | 71..=91) => {
assert_eq!(result_cell.fg, Color::Blue);
}
// state, status, cpu, memory column of the first row
(1, 18..=70) => {
assert_eq!(result_cell.fg, color);
}
// state, status, cpu, memory column
(2..=3, 4..=77) => {
assert_eq!(result_cell.fg, Color::Green);
}
// rx column
(1..=3, 92..=101) => {
assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193));
}
// tx column
(1..=3, 102..=111) => {
assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140));
}
_ => assert_eq!(result_cell.fg, Color::Reset),
}
}
}
}
#[test] #[test]
/// When container is paused, correct colors displayed /// When container is paused, correct colors displayed
fn test_draw_blocks_containers_paused() { fn test_draw_blocks_containers_paused() {
@@ -1662,6 +1663,7 @@ mod tests {
super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state); super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state);
}) })
.unwrap(); .unwrap();
check_expected(expected, w, h, &setup, Color::Red); check_expected(expected, w, h, &setup, Color::Red);
} }
@@ -1741,6 +1743,7 @@ mod tests {
super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state); super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state);
}) })
.unwrap(); .unwrap();
for (row_index, result_row) in get_result(&setup, w) { for (row_index, result_row) in get_result(&setup, w) {
let expected_row = expected_to_vec(&expected, row_index); let expected_row = expected_to_vec(&expected, row_index);
for (result_cell_index, result_cell) in result_row.iter().enumerate() { for (result_cell_index, result_cell) in result_row.iter().enumerate() {
@@ -1752,23 +1755,23 @@ mod tests {
assert_eq!(result_cell.fg, Color::LightCyan); assert_eq!(result_cell.fg, Color::LightCyan);
} }
// name, id, image column // name, id, image column
(1..=3, 4..=14 | 79..=99) => { (1..=3, 4..=17 | 74..=94) => {
assert_eq!(result_cell.fg, Color::Blue); assert_eq!(result_cell.fg, Color::Blue);
} }
// state, status, cpu, memory column of the first row // state, status, cpu, memory column of the first row
(1, 15..=78) => { (1, 18..=73) => {
assert_eq!(result_cell.fg, Color::LightGreen); assert_eq!(result_cell.fg, Color::LightGreen);
} }
// state, status, cpu, memory column // state, status, cpu, memory column
(2..=3, 15..=78) => { (2..=3, 18..=73) => {
assert_eq!(result_cell.fg, Color::Green); assert_eq!(result_cell.fg, Color::Green);
} }
// rx column // rx column
(1..=3, 100..=109) => { (1..=3, 95..=104) => {
assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193)); assert_eq!(result_cell.fg, Color::Rgb(255, 233, 193));
} }
// tx column // tx column
(1..=3, 110..=119) => { (1..=3, 105..=114) => {
assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140)); assert_eq!(result_cell.fg, Color::Rgb(205, 140, 140));
} }
_ => { _ => {
@@ -1802,8 +1805,10 @@ mod tests {
super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state); super::containers(&setup.app_data, setup.area, f, &fd, &setup.gui_state);
}) })
.unwrap(); .unwrap();
check_expected(expected, w, h, &setup, Color::Red); check_expected(expected, w, h, &setup, Color::Red);
} }
// ********** // // ********** //
// Logs panel // // Logs panel //
// ********** // // ********** //
@@ -2374,7 +2379,7 @@ mod tests {
assert_eq!( assert_eq!(
result_cell.fg, result_cell.fg,
match result_cell_index { match result_cell_index {
(2..=122) => Color::Black, (4..=124) => Color::Black,
_ => Color::White, _ => Color::White,
} }
); );
@@ -2406,7 +2411,7 @@ mod tests {
assert_eq!( assert_eq!(
result_cell.fg, result_cell.fg,
match result_cell_index { match result_cell_index {
(2..=62) => Color::Black, (4..=64) => Color::Black,
_ => Color::White, _ => Color::White,
} }
); );
@@ -2441,9 +2446,9 @@ mod tests {
assert_eq!( assert_eq!(
result_cell.fg, result_cell.fg,
match result_cell_index { match result_cell_index {
0 | 1 => Color::White, 0..=3 | 125..=139 => Color::White,
// given range | help section // given range | help section
x if range.contains(&x) || (123..=139).contains(&x) => Color::White, x if range.contains(&x) => Color::Gray,
_ => Color::Black, _ => Color::Black,
} }
); );
@@ -2452,40 +2457,32 @@ mod tests {
}; };
// Name // Name
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 1..=14, (Header::Name, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 1..=17, (Header::Name, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 1..=14, (Header::Name, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 1..=17, (Header::Name, SortedOrder::Desc));
// state // state
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 15..=26, (Header::State, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"],18..=29, (Header::State, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 15..=26, (Header::State, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 18..=29, (Header::State, SortedOrder::Desc));
// status // status
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 27..=47, (Header::Status, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 30..=41, (Header::Status, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 27..=47, (Header::Status, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 30..=41, (Header::Status, SortedOrder::Desc));
// cpu // cpu
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 48..=57, (Header::Cpu, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"],42..=50, (Header::Cpu, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 48..=57, (Header::Cpu, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"],42..=50, (Header::Cpu, SortedOrder::Desc));
// memory
// mem test(&[" name state status cpu memory/limit ▲ id image ↓ rx ↑ tx ( h ) show help"], 51..=70, (Header::Memory, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 58..=77, (Header::Memory, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 51..=70, (Header::Memory, SortedOrder::Desc));
test(&[" name state status cpu ▼ memory/limit id image ↓ rx ↑ tx ( h ) show help "], 58..=77, (Header::Memory, SortedOrder::Desc));
//id //id
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 78..=88, (Header::Id, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 71..=81, (Header::Id, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 78..=88, (Header::Id, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 71..=81, (Header::Id, SortedOrder::Desc));
// image // image
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 89..=98, (Header::Image, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 82..=91, (Header::Image, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 89..=98, (Header::Image, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 82..=91, (Header::Image, SortedOrder::Desc));
// rx // rx
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 99..=108, (Header::Rx, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 92..=101, (Header::Rx, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 99..=108, (Header::Rx, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 92..=101, (Header::Rx, SortedOrder::Desc));
// tx // tx
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 109..=118, (Header::Tx, SortedOrder::Asc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 102..=111, (Header::Tx, SortedOrder::Asc));
test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "], 109..=118, (Header::Tx, SortedOrder::Desc)); test(&[" name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"], 102..=111, (Header::Tx, SortedOrder::Desc));
} }
#[test] #[test]
@@ -2497,6 +2494,8 @@ mod tests {
setup.gui_state.lock().next_loading(uuid); setup.gui_state.lock().next_loading(uuid);
let fd = FrameData::from((setup.app_data.lock(), setup.gui_state.lock())); let fd = FrameData::from((setup.app_data.lock(), setup.gui_state.lock()));
let expected = [" ⠙ name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help"];
setup setup
.terminal .terminal
.draw(|f| { .draw(|f| {
@@ -2504,8 +2503,6 @@ mod tests {
}) })
.unwrap(); .unwrap();
let expected = [" ⠙ name state status cpu memory/limit id image ↓ rx ↑ tx ( h ) show help "];
for (row_index, result_row) in get_result(&setup, w) { for (row_index, result_row) in get_result(&setup, w) {
let expected_row = expected_to_vec(&expected, row_index); let expected_row = expected_to_vec(&expected, row_index);
for (result_cell_index, result_cell) in result_row.iter().enumerate() { for (result_cell_index, result_cell) in result_row.iter().enumerate() {
@@ -2514,7 +2511,7 @@ mod tests {
assert_eq!( assert_eq!(
result_cell.fg, result_cell.fg,
match result_cell_index { match result_cell_index {
(2..=122) => Color::Black, (4..=124) => Color::Black,
_ => Color::White, _ => Color::White,
} }
); );
@@ -3412,7 +3409,7 @@ mod tests {
"│ │• •• ││ │• •• ││ │", "│ │• •• ││ │• •• ││ │",
"│ │ ││ │ ││ │", "│ │ ││ │ ││ │",
"╰───────────────────────────────────────────────────────────────╯╰───────────────────────────────────────────────────────────────╯╰────────────────────────────╯", "╰───────────────────────────────────────────────────────────────╯╰───────────────────────────────────────────────────────────────╯╰────────────────────────────╯",
" Esc clear ← by → Name Image Status All term: r_1 " " Esc clear ← by → Name Image Status All term: r_1 ",
]; ];
setup setup
.terminal .terminal